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Issues with Calibre LVS

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bdatta

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Hello

I am using the 45nm IBM-SOI toolkit provided by MOSIS for my custom design with Cadence Virtuoso. Right now i am working on the layouts of my design. I am using the Calibre tool-suite for DRC/LVS/extraction.
For a simple inverter although my design is DRC clean when i try to run an LVS i find that the tool is not picking up the ports in the layout. This after I had generated everything (pcells & IO pins) using the 'generate from source' option in LayoutXL & connecting them carefully as per the net connections indicated by the tool-itself (layoutXL highlights incomplete nets as all are aware). I tried changing pin-names but that doesnt have any effect.
Am i missing some step? I am selecting the layout vs netlist option for LVS (there by default). Any suggestions will be appreciated.

Thanks
Basab
 

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