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Simulate netlist with Modelsim

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thanhtri_pc

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Hi all,
My name Tri. I am studying SoC subject and I have a senior project. It name "Design simple processor". I just wrote RTL coding, simulated functions and built gate-level netlist using Buildgate tool. It run well and I have the netlist. According to design flow, The next step is netlist simulation with Modeling to compare to RTL coding, but i don't know how to simulate this netlist. Could you show me (step by step)?
Many thanks
 

Hi,
I have gate-level netlist (using design compiler tool of Cadence) and SDF. I dont have manual. Coud you send it to me?
Many thanks,
 

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