Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What does report_timing do ?

Status
Not open for further replies.
V

vivek_p

Advanced Member level 4
Joined
Feb 16, 2010
Messages
115
Helped
10
Reputation
24
Reaction score
9
Trophy points
1,298
Activity points
2,009
Is the path which we get when "report_timing" command is entered in Design Compiler , the critical path of the design?

When I synthesised the design , I got data required and arrival time as 16 ns

I synthesised the design again after an addition of a latch. Then I got the "latch path" when I entered "report_timing". The data required and arrival time is 4
ns

When I checked the old path using report_timing -from ... -to I got timing as 16

Why is it so? Doesn't "report_timing" give critical path or else is it an exception when latches are synthesised?
 

report_timing

report_timing shows the most critical path (it may show the most critical path for each clock group)

critical path is defined as worst negative slack, which is the difference between data required and arrival time. When you time with latchs, time borrowing may happen and your required and arrival times will be the same and slack will be 0. If this is the case, this path isn't neccessarily your most critical path. You can check more paths like this:

report_timing -path end -max_paths 100
 

    V

    vivek_p

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top