Which is better for hardware simulation, Verilog or VHDL?

Hello,

I am a beginner to the hardware simulation: what I have to use: verilog or vhdl? and what is the best free program for each?

Thanks in advance

Re: Verilog or VHDL

I take the question,because you are a beginner .This has been debated over and over in this forum .Vhdl is more popular in europe .verilog is commonly used in north america.
Vhdl is closer to Ada .verilog is more like c language . Both are simulation languages .there is some tricks to know to use them for synthesis .
I will end my advice saying . First i assume that you have some engineering backgroud in electronics .So you must know C language . So you should be able to learn verilog very easly . Then LEARN VHDL ...learn BOTH !

Re: Verilog or VHDL

Both of these languages have advantages and disadvantages, but IMHO, Verilog is better for those who already know C or C++.

If you already know C then,perhaps you should stick with Verilog. Don't worry about choosing the right language. Both languages are strong and will get the job done.

Learning both is tedious and brings no real advantage, unless you really need it.

Re: Verilog or VHDL

Hi!

I want to add up something. If I am not wrong you also asked as what software or development tools you need?

If you are working with Xilinx FPGAs then you will have to download the development and simulation tool from xilinx. that is Xilinx ISE 11 and thats free the starter version you can download it from
www.xilinx.com

Otherwise if you are going to deal with Altera's FPGAs then you should download Quartus II software from
www.altera.com

But a better simulation tool is MODELSIM thats also free (starter version) and you can download it from
www.model.com, otherwise you can also download it from Xilinx website that is more supportive for Xilinx ISE webpack.

Best regards,
Awais

Re: Verilog or VHDL

verilog is easy to learn at first.
vhdl take some time to learn.

so ,go for verilog .

get the hdl ideas and grasp it. then you can decide afterwards.

irrespective of what language you choose ,
it is of no use , unless you write the code by yourself and use a simulator
to get the cocept concrete.

soil your hand by writing lots of basic hdlcode and simulate and simulate and simulate ....

do not choose the simulator which takes lot of space for your hard disk and takes long time to learn the simulator working innards...

chhose a simple simulator with a simple waveform viewer.
that is enough for learning first .

do not concentrate on 'fpga' development in the beginning .
you will not know where you are .

practice is the best course for learning .

learn 'hdl ' and not the tools .
present tools are monsters even for basic learning .

srizbf
4thmay2010

Re: Verilog or VHDL

srizbf said:

learn 'hdl ' and not the tools .
present tools are monsters even for basic learning .

srizbf
4thmay2010

Click to expand...

srizbf is absolutely rigth !!! These tools are for professionals and beginners have a lot a trouble learning how to use them! Took me days before compiling something sucessfully in Xilinx's Webpack, when I started.

Re: Verilog or VHDL

So, I have to begin with Verilog, the easier one. Your posts were helpful.

Thank you all.

Re: Verilog or VHDL

sent me come important interview question in verilog?

what is the difference between intra and inter delay in verilog?