Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[Help]Frequency divider to give 1ms

Thread starter didoe
Start date Apr 27, 2010

Status: Not open for further replies.

Apr 27, 2010

#1

D

didoe

Newbie level 4

I'm a new on VHDL and FPGA. I need code frequency divider from 50MHz defaul to give 1ms. Pls help me. Thanks !

Status: Not open for further replies.

Similar threads

N
Frequency Divider from Counter module - verilog
- Started by natdon11
- Mar 11, 2022
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
S
can one input clock port be connected to two MMCM for different frequency out?
- Started by skyworld_cy
- Dec 22, 2022
- Replies: 5
PLD, SPLD, GAL, CPLD, FPGA Design
S
[HELP] Looking for solution manual to Verilog Digital System Design by Navabi
- Started by seacow5487
- Apr 2, 2023
- Replies: 0
PLD, SPLD, GAL, CPLD, FPGA Design
N
Add EMIF IP to VHDL code
- Started by nelky22
- Mar 16, 2024
- Replies: 5
PLD, SPLD, GAL, CPLD, FPGA Design
L
Delay Line Time To digital Converter
- Started by Lizwi
- Mar 3, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top