Looking for docs about low power comparator design

comparator design

can someone suggest some good reading material to design a low power comparator(ANALOG)
with a resolution of 30uv

Re: comparator design

More details would help: For example, do you need a latched comparator (controlled by a clock signal) or an asynchronous comparator? In how much time is it supposed to decide ? Is it to be integrated or to be built with discrete devices ?

Re: comparator design

It is to be used for algorthmic ADC ..it should have a resolution of 30uV ...it is asynchronous..i'am working at 30kHZ....we will be using 1.6um cmos

Re: comparator design

Are you sure that you need a asynchronous comparator? Usually the comparators used in the ADCs work synchronously with the clock signal.

If it is a synchronous comparator (controlled by a clk signal) you should use a regenerative structure, which employs positive feedback. There are several known offset cancellation techniques.

If it is asynchronous you basically have to use a high-gain amplifier (this should not be a problem since the circuit is very slow).

You can check the attached file for techniques of reducing the offset.

Hope this helps
Regards

Re: comparator design

i made a mistake
i need a synchronous comparator...
the key issue is getting the resolution right(30uV)...
the input voltage range is from 0-2V.
if i use a pmos input stage it does not wokr for voltages greater then 1.
if i use a nmos input stage then it does work for voltages smaller then1volt..
is there any way i can club both the nmos and pmos input stage????

Re: comparator design

To get very low offset voltages you must probably use several pre-amplifiers before the latched comparator itself. These must have a gain high enough to make the input referred offset voltage of the latched comparator negligible, and you must use switched capacitor techniques to store the offset of the pre-amplifiers. These kinds of techniques are described in the document I posted before.

It is not a good idea to have both PMOS and NMOS input differential pairs, because then the offset voltage will depend on the common-mode of you input voltage (I’m assuming differential input here). Once again, if you use a switched capacitor input network, you can have large input swing, while the common-mode input voltage of your diff pair is always the same (the VCM at which you applied in the sampling phase to the input of the comparator).

Re: comparator design

there is an ieee paper on a 2v rail to rail micropower cmos comparator ...this design works for both low and high voltages the power consuption is in the range of nano watts....has a resolution of 30u...
the link to it is **broken link removed**

Re: comparator design

I just had a look at that paper, but it reports and expected offset voltage of 6 mV ....

Regards

comparator design

LMC7211
Tiny CMOS Comparator with Rail-to-Rail Input and
Push-Pull Output

Re: comparator design

I think you need design an offset cancellation comparator. There are two types offset cancellation method. One is IOS ,the other is OOS. They all need store capacitor and clock period for offset cancellation. And you need calculate the minium value of your offset , you must consider add how many stages preamplifier. You can see this book:"Principles of Data conversion system design" Behzad Razavi.

Re: comparator design

You need to do the offset cancellation for both preamplifier and also the latch. Better to do Output offset cancellation for preamplifier and input offset cancellation for latch. I am attaching a file. Here the offset cancellation upto 300uV at 5MHz is discussed. Since your frequency of operation is less you can acheive more I guess.