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frequency divider by 2 in Verilog?

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jason7361

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Can anyone give me a divider which frequency equal clock divider by 2 in Verilog?

The divider will create by a D flip flop.

Thank you.
 

Simply invert the output on each clock cycle:
always @(posedge clk)
q <= ~q;
 

always@(posedge clk or negedge rst)
if(rst)
q<= '0';
else
q<= ~q;
 

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