verilog behavioral synthsesis problem

hello all,
I have two questions-
1.) I have written a behavioral code in verilog that uses some internal registers. During synthesis warning is generated that the signal is assigned but never used in the program so it will be trimmed during optimization part.Will it produce an error in the fpga kit.
2.)there are two ports in my code each of 13 bits width. How can I assign these two ports in FPGA kit. I am using nexys 2 board.

with regards-
victor

1. May or may not be critical. Maybe you have some regs you declared but never had any need for and forgot to take it out of your code. Or maybe there is some redundancy. You can post your code if you want a definite answer or you can always test your design.

2. You use ISE constraints editor. It will allow you to tie ports from your verilog module to physical pins on the FPGA board.

thank you very much for replying.I am posting my code which I took from somewhere and modified it....
module add(
input wire signl, sign2,
input wire [3] expl, exp2,
input wire [7] fracl, frac2,
output reg sign_out ,
output reg [3] exp_out ,
output reg [8] frac_out
) ;

// signal declaration
// suffix b,s,a,n for
// big ,small ,aligned , normalized number
reg signb,signs;
reg [3] expb,exps,expn,exp_diff;
reg [7] fracb,fracs,fraca,fracn,sum_norm ;
reg [8] sum;
// body
always @*
begin
// 1st stage : sort to find the larger number
if ( {expl,fracl} > {exp2,frac2})
begin
signb=signl;
signs=sign2;
expb=expl;
exps = exp2;
fracb=fracl;
fracs=frac2;
end
else
begin
signb=sign2 ;
signs=signl;
expb =exp2 ;
exps =expl ;
fracb =frac2 ;
fracs =fracl ;
end

// 2nd stage : align smaller number
exp_diff= expb - exps ;
fraca=fracs >> exp_diff ;
// 3rd stage : add / substract
if(signb == signs )
sum ={1'b0 ,fracb}+{1'b0,fraca} ;
else
sum={1'b0,fracb}-{1'b0,fraca};
// form output
sign_out = signb ;
exp_out = expb ;
frac_out =sum;
end
endmodule

Added after 1 minutes:

and for the 2nd problem that was assigning the pin. I am using nexys two board n I think there are only 8 switches through which I can give input. But in this code you can see that I need two input of 13 bits wide. So how can I do that ? thnx in advance..

It would help if you can post the exact warnings which makes it easier to pin-point the regs.

And for inputs, you have several options. You can make use of the eight switches and do bit shifting or masking. Or you can use a VIO core from chipscope if you have access to it.