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How to find gate width for irregular MOS shapes?

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ahmad_abdulghany

ahmad_abdulghany

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Hi,

For simple rectangular MOS transistors, it's easy to identify width and length depending on direction of current flow.

If you've complex irregular MOS transistor (not like a spider :D but mostly like a rectangle having many glitches from one or both sides), is there a scientific method in this case to define W and L? Sometimes current flow is still in two orthogonal directions but we've different crossing areas to current flow.

I have seen before a paper talking about big W/L ratio transistors with irregular shapes, but I cant recall where did i see.

Any ideas or papers talking about that issue?

Thanks,
Ahmad
 

ahmad_abdulghany said:
Any ideas or papers talking about that issue?
Click to expand...
An appropriate extraction rules file can achieve this (by extraction). Search for "extraction rule" and, perhaps, "waffle", like, e.g. this one. Not sure if it is helpful.
 
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ahmad_abdulghany said:
Hi,

For simple rectangular MOS transistors, it's easy to identify width and length depending on direction of current flow.

If you've complex irregular MOS transistor (not like a spider :D but mostly like a rectangle having many glitches from one or both sides), is there a scientific method in this case to define W and L? Sometimes current flow is still in two orthogonal directions but we've different crossing areas to current flow.

I have seen before a paper talking about big W/L ratio transistors with irregular shapes, but I cant recall where did i see.

Any ideas or papers talking about that issue?

Thanks,
Ahmad
Click to expand...

From the end-user (designer) perspective, the LVS extraction does the gate width calculation for you (see erikl's post).

From device physics viewpoint, the gate width is an ill-defined parameter, in general case (for example, when gate has an O-shape - is it internal or external circle that defines the gate width?).

Sometime, device compact models are not scalable with respect to the gate width (they define current per one cell), then the concept of the gate width does not have sense at all.
 

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