VHDL: Problem with pulse generator

Hey, I am new to VHDL programming and I am doing a general hobby project in vhdl but it got a module which seems very difficult for me understand at this time. could anyone look over it and let me know what should I be doing and hopefully provide a code for this please.

Module 3: Pulse Generator
In this module, you will design a pulse generator (Gen_pulse block) to generate the
necessary control signals at a low frequency, approximately 1 Hz. Refer to the
timing diagram below:
Figure
5
An entire cycle generated by the Gen_pulse block, starts on the rising edge of the
clock with the reset pin high (reset is active low in this application) and ends when
the internal counter reaches its maximum. A high pulse of Capt_En indicates the
start of the cycle, and it is high for one clock period. In the middle of the cycle, the
Write_En
signal
should
go high for one clock period. The third control signal
Show_Rand is high for half of the total cycle. A good value for the length of the
generated cycle is 1 second. Since the VirtexII pro runs at a clock frequency of 100
MHz (a clock period of 10ns), you must calculate the maximum value of the
internal counter required for this pulse generator.
The description and purpose of the control signals:
• The Capt_En is connected to the capture block. This signal will be
responsible for placing a random number at the output of the capture block.
This random number will later be used by the LED driver to display the
number, but will also be used by the FIFO, to temporarily store the value for
comparison with the user input.
• To write the value to the FIFO, the Write_En signal generates a pulse after
the random value is brought to the output of the capture block. This pulse is
generated in the middle of the period, and goes to the wr (write pin) of the
FIFO.
• Combining these two signals results in the third signal, the Show_Rand
signal. This signal is used by the LED driver. A high value indicates that the
value from the capture block should be displayed on the LEDs, a low value
indicates the value should not be displayed. This creates a blinking effect on
the LEDs and is necessary in the case when two successive random numbers
are the same. A period where no LEDs are blinking signals the user that the
next value will be displayed.

Verify the functionality of both the block using a testbench.

Did u solve the problem? i am new to VHDL too

Yea I got it.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Gen_Pulse is
Port ( Clock : in STD_LOGIC;
Show_Rand : inout STD_LOGIC :='0';
Write_En : out STD_LOGIC:='0';
Capt_En : out STD_LOGIC:='1');
end Gen_Pulse;

architecture Behavioral of Gen_Pulse is

signal count : integer :=1;
begin
process(Clock)
begin
if(Clock'event and Clock='1') then
count <=count+1;
if(count = 10) then
Show_Rand <= not Show_Rand;
count <=1;
end if;
if(Show_Rand = '0' and count = 10) then
Write_En <= '1';
else
Write_En <= '0';
if(Show_Rand = '1' and count = 10) then
Capt_En <= '1';
else
Capt_En <= '0';
end if;
end if;
end if;
end process;


end Behavioral;










tb





LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Gen_Pulse
PORT(
Clock : IN std_logic;
Show_Rand : INOUT std_logic;
Write_En : OUT std_logic;
Capt_En : OUT std_logic
);
END COMPONENT;


--Inputs
signal Clock : std_logic := '0';

--BiDirs
signal Show_Rand : std_logic;

--Outputs
signal Write_En : std_logic;
signal Capt_En : std_logic;

-- Clock period definitions
-- constant Clock_period : time := 1us;
-- constant Show_Rand_period : time := 1us;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: Gen_Pulse PORT MAP (
Clock => Clock,
Show_Rand => Show_Rand,
Write_En => Write_En,
Capt_En => Capt_En
);

clock1_process rocess
begin
Clock <= '0'; --reset<='1';
wait for 10ns;
Clock <= '1'; --reset<='1';
wait for 10ns;
end process;


END;