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PLL delay in frequency multiplication

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buenos

buenos

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PLL delay

hi

is there a way to phase lock the PLL input to its output when using the PLL for frequency multiplication?
can we guarante the input and output edges to be in a fixed relationship in the aspect of static timing?
does it depend on the PLL or FPGA chip, or we never can lock it?

I am asking this to figure out if it is really necessary to use asynchronous FIFOs for SERDES transmitters.
 

Re: PLL delay

Usually, the PLL output phase can be adjusted in a way, that synchronous transfers between in- and output clock domains are
possible. This applies at least for several 100 MHz clock speed. At higher frequencies, the margin is possibly too small to
achieve reliable timing closure.
 

PLL delay

is there some appnote describing this? or is it mentioned for example in a xilinx datasheet?

For a 3.1Gbps 8b10b encoded interface, we would have a 310MHz parallel bus going to the serdes...
I am reading a book that references to an IBM serdes IP core that uses FIFOs for Tx.
 

Re: PLL delay

For Gbit speed, you have to use dedicated hardware SERDES in any case. So your question is actually addressing the specfic hardware
design of your target FPGA. The transmitter path possibly includes a phase compensation FIFO. In this case, your original question
if it's "really necessary to use it" doesn't apply for a user.
 

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