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How to make RAM/ROM memory in IBM 65nm process

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chickenvlsi

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Hi everyone,
I am using Cadence with CMOS10LPE IBM library (65nm).
my design needs a ROM (1K, 10bit) and a RAM (4K, 10BIT).
In order to make those ROM and ROM, I think the most straightforward way is to design their CMOS circuits, simulate them and then do layout. However, this method would take me a lot of time and I am afraid that I will not be able to meet the deadline of my project.

Fortunately, I just came to know that, if we use a memory compiler, we can realize the memory we need in a very short time. But there are some questions that I can not answer myself. Could you please clarify them to me?

1. Could you please recommend me some good Memory Compilers?
2. Could you explain a bit about the operating mechanism of a typical memory compilers? What is its inputs and outputs?
3. I am currently using 65nm cmos10lpe from IBM and Cadence tool. That's all the resource I have at the moment. Could you please let me know what I need to do in order to make a ROM/RAM with the help of a Memory Compiler ?
4. Could you please send me some good documents about memory compilers?
Thank you very much.
I am looking forward to hearing from you
 

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