how to instantiate a PLL in Actel Libero

Hi

I am working with Actel Liber and ProASIC3 FPGA.
I need to include a PLL in my VHDL code.
what is the instantiation template for this? where is it written down?
for xilinx devices, it is i think in the language templetes, but in actel libero, i could not find it.

Added after 22 minutes:

they mention a program "smartgen" to use for this.
but how do i launch that program? maybe it is not installed for me, but i also can not find a smartgen installer on the internet...

SmartGen is a legacy macro generator tool from Actel that can be accessed using the Catalog in Libero IDE Project Manager. You can generate any PLL from the Libero IDE Catalog. For your specific case, you can generate a PLL for ProASIC3 family in the VHDL format, as follows:
1. Create a new Libero IDE project for ProaASIC3 family in VHDL format.
2. Expand the Clock & Management group in the Catalog pane.
3. Double click “PLL- static”
4. Select the configuration of the PLL block in the “Static PLL: Create Core” dialog. The configuration is based on your requirements
5. Click the “Generate” button, at the right bottom of the screen.
6. You will be prompted with the “Generate Core” dialog; assign a name to your core (e.g. pll1 in the screenshot below), and click OK.
7. The PLL block (e.g. pll1, see attached screenshot) will be created and displayed in the Libero IDE Hierarchy pane. You can instantiate it from here using your HDL code or SmartDesign.

hi

thanx.

actually i could not start the smartgen from the catralog, but i found the smartgen.exe in the install dir, so i have sortred it out.

another problem is that when i had 2 global clocks coming ionto GFxx global pins, then the P&R program stopped with an error, because i had to use the PLL in the F global on internal signals. i had to move those clocks to GAxx and GBxx, so the P&R could complete.
this does not make much sense to me. i thopught the rule is that for any GXYZ, only one of the Z pins can be used. but it seems that using the internal PLL on internal signals create more rules.

Hi there,

I would suggest that you contact tech support, so they can resolve your inquiry. Please email tech@actel.com and reference your case number (1-40241360). Make sure you include the following information in your email: your name, company name, phone number, email, and location.

Regards,

Joan

hi

thanks, i have found the solution:
GFAx pins are not available for on-board input clocks if the PLL is used. so i had to use GFBx and GFCx for those. GA,GB,GD,GE are not full-chip global pins.
these information can be derived from the datasheet, but it is not written in a very obvious way.
those people who use actel PFGAs are more likely to design the board first then do the FPGA code, so it would be good to make the global pin usage more clear. it would be different for example for a xilinx virtex-5 with high speed interfaces.