bibidibabidibup
Newbie level 2
Hello everyone,
im newbie in here and this is my first question. here we go
this is a two bit fulladder homework for ise xilinx
when im trying to test with UUT i see summary 0 is ok but summary-1(s0 s1) is that Z because of never used a1 and b1
whats wrong with it?
note:this code works for 1 bit adder
Main programme:
Test programme
im newbie in here and this is my first question. here we go
this is a two bit fulladder homework for ise xilinx
when im trying to test with UUT i see summary 0 is ok but summary-1(s0 s1) is that Z because of never used a1 and b1
whats wrong with it?
note:this code works for 1 bit adder
Main programme:
Code:
module Add_full_0_delay(sum,c_out,a,b,c_in);
output [1:0]sum;
output c_out;
input [1:0] a,b;
input c_in;
wire w1,w2,w3;
Add_half_0_delay M1(w1,w2,a,b);
Add_half_0_delay M2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule
module Add_half_0_delay(sum,c_out,a,b);
output sum,c_out;
input a,b;
xor M1(sum,a,b);
and M2(c_out,a,b);
endmodule
Code:
module t_full();
wire [1:0] sum;
wire c_out;
reg [1:0] a;
reg [1:0] b;
reg c_in;
Add_full_0_delay(sum,c_out,a,b,c_in);
initial begin
#100 $finish;
end
initial begin
//run through a series of numbers
a=2'b00;b=2'b00;c_in=1'b1;
#10a=2'b01;b=2'b00;c_in=1'b1;
#10a=2'b01;b=2'b11;c_in=1'b1;
#10a=2'b01;b=2'b11;c_in=1'b1;
#10a=2'b11;b=2'b11;c_in=1'b1;
#10a=2'b11;b=2'b11;c_in=1'b1;
#10a=2'b01;b=2'b00;c_in=1'b0;
#10a=2'b01;b=2'b11;c_in=1'b0;
#10a=2'b01;b=2'b11;c_in=1'b0;
#10a=2'b11;b=2'b11;c_in=1'b0;
#10a=2'b11;b=2'b11;c_in=1'b0;
#10$finish;
end
endmodule