# how to equate the rise time and fall time of cmos logic gate

1. ## how to equate the rise time and fall time of cmos logic gate

hi,there
i am working clock circuit with cmos logic gate,i.e,inverter,nand2,nand3,nor2,and the high level is 1.2v with low level 0v.
i want to set the rise time and fall time of them to a equal value.
so i short the input of them and give a vdc input and run the dc analysis while sweeping the input from 0 to 1.2v.
then i change the W/L of the transistor until i find that the cross point of input and ouput is nearly 0.6v on both of them.
next i test the rise/fall time of them,but only to find that they are not equal.
then i change the W/L again to set the rise/fall time equal,but find that the cross point of input and output is far away from 0.6v.

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2. ## Re: how to equate the rise time and fall time of cmos logic

Originally Posted by urian
... i change the W/L again to set the rise/fall time equal,but find that the cross point of input and output is far away from 0.6v.
The latter method, if you want equal rise/fall times. It's not necessary (nor possible) to get a mid cross point in this case, as the threshold voltages of both FETs are different.

1 members found this post helpful.

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3. ## how to equate the rise time and fall time of cmos logic gate

thanks,erikl,i got it

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