What's the difference between DFT and BIST?

DFT and BIST

A friend of mine asked the following question:
Is BIST another form of DFT?
An answer that I received (too confuse to me) is:
BIST and DFT are the same but difference in protocol.

Can some body clarify the differnce(s) of these terminologies.

Thanks in advance,

DFT and BIST

Of course, they are different!

DFT means Design-for-Test - it is a methodology of IC design which simlify further IC testing (like scan-path insertion etc.)

BIST means Built-in Self Test - usually it has a form of small module which additionally placed on chip and which can run different tests, like pseudo-random, pseudo-exhaustive test, memory test etc.

They can work together, so IC can be designed following DFT rules and can contain BIST module which will use DFT resources to perform tests. Or it can go without BIST.

Hope it helps!

Ace-X.

Re: DFT and BIST

DFT: Design-for-Test
BIST: Built-in self-test
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Yes. They are different.
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But I think BIST is one kind of DFT.
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"Design"-for-Test does not only contain scan chain insertion for ATPG,
but also contain BIST.

BIST, no matter Memory BIST or Logic BIST, is one way of "design" for test.
--------------------------------------------------------
DFT is some kind of concept.
And there are lots of methods to implement it.

DFT and BIST

BIST consists of
*)DUT
*)PRPG-> Psuedo random pattern generator
*)Response compactor
*)Comparator
*)Memory for storing the expected results

PRPG pumps in random data to the DUT. DUT response is compacted and compared with expected response for corresponding to that particular input. The expected results will be stored in ROM.

Used for
*) Field tests
*) At-speed tests
*)Reducing ATE Costs etc

Bist is one type of DFT

others are scan insertion,jtag bounday scan etcc

Re: DFT and BIST

joe2moon said:

...
But I think BIST is one kind of DFT....

Click to expand...

whizkid said:

...
Bist is one type of DFT....

Click to expand...

Sorry guys, but I can't agree about it. Just simple example: someone can design SoC with memory BIST (it does not require any scan-path insertion, BILBO etc.) on chip but without any techniques, that are considered as a part of DFT methodology.

Of course, practically you are right, because all modern IC with BIST follows the DFT rules, but it is not right from the theoretical point of view.

Ace-X.

Re: DFT and BIST

Thanks Guys,
It is not quite clear about the differences between DFT and BIST. But any way, thanks all about your time and efforts.

DFT and BIST

I agree with the point of "BIST is a kind of DFT".

DFT and BIST

In DFT we will be using BIST

Re: DFT and BIST

the DFT should include: internal-scan, memory bist, logic bist.

Re: DFT and BIST

DFT is design for test BIST is Built in self test
DFT is test by scan chain
BIST is built in pattern generator

DFT and BIST

DFT is so complicated, how to fix S27 DFT DRC violations in synopsys DC?

Re: DFT and BIST

Ace-X said:

joe2moon said:

...
But I think BIST is one kind of DFT....

Click to expand...

whizkid said:

...
Bist is one type of DFT....

Click to expand...

Sorry guys, but I can't agree about it. ...
Ace-X.

Click to expand...

I think BIST is one kind of DFT.
As far as know, there are three parts of DFT.
(1). Scan Technology
(2). BIST Technology
(3). IDDQ Technology

In Scan Technology, there are full-scan(like LSSD of IBM), part-scan(like DFF Scan) and boundary-scan(like BSDL language).

In BIST Technology, there are logic-bist and memory-bist primary. This is one way to make reparation for scan-test.

Re: DFT and BIST

I agree with Alexwon.
Additionally, I would think all design efforts for testing purpose (for both functional and manufacturing test) can be regard as design for test.

DFT and BIST

Funny to read posts when red is compared to green.

Once again: DFT is a methodology, it has arrived in 1960s and was developed to reduce the cost of creating tests for an IC by improving controlability and observability of the circuit under test. Scan design, ATPG, JTAG etc. - all this stuff is to simplify EXTERNAL test of IC. As to BIST - its main idea is to design a circuit, which can INTERNALLY test itself and determine whether it is good or bad.

And now, if you would get memory IC with BIST, what the DFT approaches were used to design it? Scan insertion? No! JTAG? No! Designer gets plain memory, adds memory BIST to the die and that's all.

Of course, most of modern IC are designed following DFT rules, often with BIST integrated with scan chains, but DFT and BIST are theoretically different.

Re: DFT and BIST

I think that the DFT includes BIST,SCAN_CHAIN and so on, so the BIST is a kind of DFT.

DFT and BIST

DFT is a design rule for testability,
BIST is a way for attachment of the rule.

DFT and BIST

What are the popular tools for implementing BIST?

DFT and BIST

maybe there are no confirmed boundary between dft and bist!

Re: DFT and BIST

I agree Bist is one kind of DFT. As my undestanding, any kind of circuitry we put into the chip to improve testability, is a DFT technique.

Re: DFT and BIST

hey all,
According to me....
There is NO difference between DFT (Design For Test) and BIST (Built In Self Test)....however we can put BIST under this category i.e. DFT (Design For Test)....
Why???
Answer is-- if Any SOC to be tested... during design phase of SOC......any DFT engineer will consider the testability of that SOC....either using JTAG or BIST....
Usage Model -- BIST -> when SOC has memory based architecture....then one must use BIST ...why? answer is -> before SOC starts operation in test mode we can test the internal memory architecture....and there functionality....etc.... BIST architecture is very very complex and requires more number of Gates/transistors.
there are separate registers to invoke this functioality. and easily accessible to the external users...usage limited to the Validation of that particular SOC..


in case of JTAG ---> it is simple and based around the SOC....this is required..and very useful....when SOC goes on....board (PCB)...how do we make sure that SOC is working and Board has no manufacturing issues(stuck at0,1 etc.) during assembly....with the help of JTAG Scan chain we can make sure all the pins are connected to the board....and board also has no issues.....


SO...IN My Opinion BIST is part of DFT....