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Design compiler doubts

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ashokjain

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I have started exploring design compiler and have few questions and probably more to follow. It will be great if you can help me with your thoughts on them.

1) I saw that all the existing scripts in my company had specified multicycle paths for the signals which travel across clock domains. Why not false paths?

2) All the scripts had specified output and input delays as 75% of clock period. How do we decide these values?

Thanks.
 

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