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IO pads insertion UMC 90 nm in Cadence tools

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dkg.sonu

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Hi Guys,

PLEASE HELP

I am designing a 32 bit ripple carry adder using UMC 90 nm design kit.
Please tell me how do i insert pads in my design what files i need to use.
I am using Cadence Soc encounter

thanks in advance.
 

This looks like a old posting and i am sturck exactly in the same place as you were in...

Plz let me know if you have arrived at the conclusion.
 

Dear Iohi21,

I added the pads after synthesizing my design in the verilog code generated by the rtl compiler.
You can find the type of pad as per your requirement from the library documentation.

In the new veilog file

Just add a new module eg. design_pads and instansiate the pads as u would instantiate any othe module in verilog.

When u are importing the design for placement and routing you have to include the appropriate led files and timing files which are there in the design library.
 

After you modified the netlist design import and load your design in Encounter. You can see the IO pads randomly placed around the core. Then you need to modify the IO arrangement file. You can get the format of the .io file by saving I/O file first and change it. In .io file, you need to add corner IO pads as well.
 

All the information about editing the io file is given in the Encounter user manual.
After editing the file you just have to reload the io file and click on the Reload button("Little orange button with an arrow on the shortcut toolbar.")
 

Hi dkg.sonu,
did you add the pad in your netlist manually, or there is some commands to do that?
Thanks
 

hi,

Ya, I did add them manually in the synthesized netlist.
 

It seems synopsys does have the commands to add pads, so it would be better to use that?
 

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