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square root verilog code....plzzzzzz its very urgent

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alangs

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see below code of square root of a number.....here the output is coming after finishing of 15 clock....i need this code to give output of square of a number at less number of colck (2 or 3 clocks)...can any one do this and send me the code....
:cry:
module sqrt
#(
parameter DATA_WIDTH = 8,
ANSWER_WIDTH= 8,
TRIAL_WIDTH = 4
)
(
clk,
data,
start,
answer,
done
);
input clk;
input start;
input wire[DATA_WIDTH-1:0] data;
output reg [ANSWER_WIDTH-1:0] answer;
output done;

//reg [DATA_WIDTH:0] answer;
reg busy;
reg [1:0] bit;
wire [TRIAL_WIDTH-1:0] trial;

assign trial = answer | (1 << bit);

always @ (posedge clk)
begin
if (busy)
begin
if (bit == 0)
busy <= 0;
else
bit <= bit - 1;
if (trial*trial <= data)
answer <= trial;
end
else if (start)
begin
busy <= 1;
answer <= 0;
bit <= 3;
end
end

assign done = ~busy;
endmodule
 

square root verilog code

a CORDIC core may be available from fpga's manufacture
 

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