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if you draw an nmos with its source and gate (input high/switch on)connected to Vdd, and adjust the voltage of the drain (the output), you'll see that once the drain gets higher than Vdd - Vth the nmos will turn off. This means the output can never get higher than Vdd - Vth. It's still a 1 if it's higher than VIH but if it's lower than Vdd (the ideal) we call it a "weak" one.
if you draw an nmos with its source and gate (input high/switch on)connected to Vdd, and adjust the voltage of the drain (the output), you'll see that once the drain gets higher than Vdd - Vth the nmos will turn off. This means the output can never get higher than Vdd - Vth. It's still a 1 if it's higher than VIH but if it's lower than Vdd (the ideal) we call it a "weak" one.
We need to connect the drain and gate of NMOS to VDD, and view the output at source, as the drain of NMOS must be at a higher potential than source for its normal operation.
When the source potential reaches VDD-Vth, the gate-to-source voltage Vgs become Vth. Any further increase in source potential causes the Vgs to drop below Vth. So the NMOS will turn off. But when the NMOS turns off, the source potential will drop, which will turn on the NMOS. This looks like a cycle. So the NMOS source will be pinned to VDD-Vth.
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