mytreyi
Junior Member level 3
I was implemented nand gate layout in cadence tool....is it correct or not...
one body (M1_pDiff for nmos,M1_Nwell for PMOS) is enough for all nmos(pmos) circuits in the design...
how to connect the substrate....
IN schematic all nmos body connect to the gnd,all pmos connect to the supply vdd....
just i am in starting stage.. layout in cadence..plz help me...
one body (M1_pDiff for nmos,M1_Nwell for PMOS) is enough for all nmos(pmos) circuits in the design...
how to connect the substrate....
IN schematic all nmos body connect to the gnd,all pmos connect to the supply vdd....
just i am in starting stage.. layout in cadence..plz help me...