casual
Junior Member level 2
I did a simple inverter layout & run Calibre LVS
here is the LVS extraction report
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## C A L I B R E S Y S T E M ##
## ##
## C I R C U I T E X T R A C T I O N R E P O R T ##
## ##
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REPORT FILE NAME: inverter3.lvs.report.ext
LAYOUT NAME: /app/project/CSM018IC/LVS/inverter3.calibre.db ('inverter3')
CREATION TIME: Mon Mar 8 15:21:17 2010
CURRENT DIRECTORY: /app/project/CSM018IC/LVS
USER NAME: kstan
CALIBRE VERSION: v2008.1_13.11 Fri Feb 22 15:14:30 PST 2008
WARNING: Invalid PATHCHK request "GROUND && ! POWER": no POWER nets present, operation aborted.
WARNING: Invalid PATHCHK request "POWER && ! GROUND": no POWER nets present, operation aborted.
WARNING: Invalid PATHCHK request "! POWER && ! GROUND": no POWER nets present, operation aborted.
---------------------------------------------------------------------------------------
In ERC warning:
ntap with no path to power
ptap with no path to ground
----------------------------------------------------------------------------------------
I just wonder whether is it ok or not... ?
I got LVS passed! & DRC passed!!
However i got the Warning in the LVS extraction & ERC report!!
NOTE that:
In schematic, the schematic has only in & out pin. Vdd! and gnd! are ground pins
In layout, I labeled in, out, vdd! and gnd!
Is it ok that I didnt use vdd & gnd pins in schematic?
here is the LVS extraction report
#############################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## C I R C U I T E X T R A C T I O N R E P O R T ##
## ##
#############################################################
REPORT FILE NAME: inverter3.lvs.report.ext
LAYOUT NAME: /app/project/CSM018IC/LVS/inverter3.calibre.db ('inverter3')
CREATION TIME: Mon Mar 8 15:21:17 2010
CURRENT DIRECTORY: /app/project/CSM018IC/LVS
USER NAME: kstan
CALIBRE VERSION: v2008.1_13.11 Fri Feb 22 15:14:30 PST 2008
WARNING: Invalid PATHCHK request "GROUND && ! POWER": no POWER nets present, operation aborted.
WARNING: Invalid PATHCHK request "POWER && ! GROUND": no POWER nets present, operation aborted.
WARNING: Invalid PATHCHK request "! POWER && ! GROUND": no POWER nets present, operation aborted.
---------------------------------------------------------------------------------------
In ERC warning:
ntap with no path to power
ptap with no path to ground
----------------------------------------------------------------------------------------
I just wonder whether is it ok or not... ?
I got LVS passed! & DRC passed!!
However i got the Warning in the LVS extraction & ERC report!!
NOTE that:
In schematic, the schematic has only in & out pin. Vdd! and gnd! are ground pins
In layout, I labeled in, out, vdd! and gnd!
Is it ok that I didnt use vdd & gnd pins in schematic?