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how to create sign adder using verilog code

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J_expoler2

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Hi i can't generate sign adder
----------------------------------------------------------
module AD3(D1,D2,D3,Do);
input [15:0] D1;
input [15:0] D2;
input [15:0] D3;
output [16:0] Do;
reg [16:0]Do;
always @ (D1 or D2 or D3)
Do=D1+D2-D3;
endmodule
-----------------------------------------------------------
i using Do=D1+D2-D3; but when i view RTL schmetic it show unsign adder
how to i write it
 

What compiler you use?

Using verilog 2001 compatibility?
 

Just tried with ise6.2i and my rtl schematic is just a blackbox with 3 inputs and 1 output...nothing about (un)signed....
 

8bit add 8bit can be written as follows:
wire[7:0] a,b;
wire[8:0] sum;
assign sum = {a[7], a} + {b[7],b};
 

This works in 6.1i:

module AD3(D1, D2, D3, Do);
input signed [15:0] D1;
input signed [15:0] D2;
input signed [15:0] D3;
output signed [16:0] Do;
assign Do = D1 + D2 - D3;
endmodule
 

Signed operations are supported since Verilog 2001 released. Plz confirm your synthesis tool can support the signed operation. If so, you can use the 'signed' keyword. otherwise, you may have to follow the coding style suggested by *fangll

good luck.
 

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