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Accuracy of static timing report for FPGA design

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Do I need to simulate after the place and route to make sure that the design operates at the maximum frequency reported in the static timing report ? Or is the info I get from the static report enough??

Thank you
 

Fpga design?

For the most time, the timing report is correct, because it is not using the best case for calculation.

But if you have problems,specifically timing related problem, then post layout simulation will help you possibly find those. But it is SLOW and tricky.

Best regards,
/Farhad Abdolian
 

Re: Fpga design?

It is very tricky, I keep getting wierd setup violation errors at high speed.. :S Can you tell me by time related problems.... ??

Thanks
 

Re: Fpga design?

Ok,
If you get setup violation, then it means your timing is not correct. The problem with SDF based simulation is that you need a good simulation model for all peripherals you have or else your simulation will be really difficult and not very useful.
 

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