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Post-Layout Simulation - Glitching Probelm

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nanavaras6284

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I am a student working on a Digital IC design.

I have completed the design layout using SOC Encounter and generated the verilog and sdf files from the layout design.

When I tried to simulate this post-layout netlist with NCVerilog, I see Glitching noise at the output. Please refer to the attached screenshot of the glitches which occurs exactly at the rising edge or falling edge of the signals.

The Pre-layout simulation didnot show this problem.

Can some one help me what should be done to solve this issue.
 

Register the output with a flop.
 

Hi RBB,
Thanks for the reply.
But I already have flip-flops at the output.

As u can see from the screen-shot, the digital data "audio_in[7] to audio_in[0] is very much unaffected.
The combined analog sample and hold signal (as dispalyed by NCVerilog) "audio_in[7:0]" which shows the glitches.

I am guessing this occurs due to path delay between the digital signals. Is this guess right? Is there any workaround through this problem?
 

what about the clock skew at the flop inputs?
if the flops are getting clock at different time instances, outputs of flops also changes at different time instances(which can cause glitch)
please correct me if i am wrong..
 

Thanks for the suggestion.

I have done Clock tree synthesis, which should take care of the clock skew problem.
But I will check this again.

I will try reducing my Maximum skew value and update you the results.
 

Hi,

I have a doubt in something.
Could you please tell us what is the process technology you used and the operational frequency ?
 

Sure.
I am using 0.35um technology, using AMS Hit-Kit V4.00.
The operating frequency is only 1.536 MHz maximum in this design.
 

"As u can see from the screen-shot, the digital data "audio_in[7] to audio_in[0] is very much unaffected.
The combined analog sample and hold signal (as dispalyed by NCVerilog) "audio_in[7:0]" which shows the glitches"

I dont see any glitches in audio_in[7:0]. Could you please indicate one glitch. Or, do you mean the analog signal in the figure ?
How did to you obtain it ?
 

Oh.
Let me put this correctly.
I need my output to be like audio_in[7:0].
But I am getting something like audio_in_nopad[7:0], which shows the glitches.

I am displaying the digital data bus as analog sample and hold signal in NCverilog, if that is what you meant by "how did you get that?"
 

Could you please circle in the picture one glitche ?

Are you using clock gating ?
 

Yes, please find the attached screen-shot with glitches marked with red circles.
It occurs everytime any of the bits switches.

I am not using clock gating.
 

OK I See.


I have a doubt in propagation delay.
How did you obtain that signal ?
 
My design is a Digital Filter bank which takes in a audio signal and separates that into different frequency bands. The signals are then amplified. In the output I have shown the amplification factor is one in all the bands.

The amplified signals are then combined together to get the output. Here as the gain is one, the input and the output should be the same.

Does this answer your question on How did I obtain the signal?
 

I agree with AdvaRes, that your so-called glitches are most likely simulation artefacts caused by inappropriate presentation
of the output data. Basically, the parallel output data can't be analyzed without a respective sampling clock. You don't show any
clock. But it can be clearly seen, that the "glitches" are smaller than the output word rate.

A higher resolution detail view would show this more clearly.

For simulation purposes, you can add an analog S/H function. For the real circuit, your D/A circuit must be able to reproduce
the output data without glitches. But this problem hasn't to do with digital logic behaviour.
 
oh ok. I understand now.
Thanks everyone for answering my queries.

My device does not have D/A or A/D circuit.
My input and output are both digital. I used NCVerilog waveform viewer window to show the bus as 'analog sample and hold' signal.
 

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