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File inclusion in VHDL - is it possible? How to do this?

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raghava

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HI all,

In verilog a file could be included by
`include "file.v" in some .v file. In the same way can we do this in VHDL.

If so, can anybody share their knowledge how.??

Regards
 

Re: File inclusion in VHDL - help needed

HI,

I am expecting answers

Regards
 

File inclusion in VHDL - help needed

The feature is not provided by the VHDL standard. May be some design tools offer it as private enhancement, but I'm not aware of.
 

Re: File inclusion in VHDL - help needed

there are other ways available in VHDL to archive same thing....

i.e. you can use TEXTIO library and its functions/procedures to read/write the file and if you have some other component defined in other file then you can simply use component instantiation in top module.
 

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