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PWM in Verilog HDL - design does not work but no errors

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Aurixious

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I am trying to make a PWM to the specifications in the attached word document. I get no errors or warnings in my my synthesis or implementation, but the design does not work. When my program/enable switch is high, pressing the buttons does not increment or decrement.

The word document is located in the zip file and is called Lab4.doc.

The initial clock is 50MHz and is divided down to approx. 12KHz.

I'm using a Spartan 3E board.
 

Re: PWM in Verilog HDL - help needed

Never mind I have it working now.
 

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