problems with clocks (i think)

Hello everybody..

I'm doing a FIR filter in a spartan 3e FPGA, but doesn't work as I want.
the problem is a little strange.

every time that I generate a bit file, the behavior of the system is different!...
for example...
I generated a bit file. I charged it. I put, as input tho the filter, a constant value and the filter give a constant value A. Then I generated the bit file again, put the same input and this time the result was a constant value B..

I have 4 warning related to clocks. The warning says that the system uses general resources to route the clocks.

I'm using a DCM to generate all the clocks in the system..
Could, the problem, be relationed with the warnings?

I was thinking using two DCM's and reduce the fan out of each clock
Is that a good idea?

ah.. and.. why I think that the problem is in the clock?.. because I implemented the FIR using clocked bit serial multipliers.

I hope that someone could help me.

Thank you for all !
greetings

first tell me how many clocks you are using... and if they are probably more than one... then sure due to them some issue is created... try to make design with single clock...