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Will DC remove un-used logic when synthesis

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yx.yang

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Hi, All:

I have a question about whether Design Compiler will remove unused logic as FPGA synthesis tool, such as XST, synplify.
For example: 1): a FF will no load; 2): define a reg with 32 bits, but just 16 bits are use. 3): Output single is not used.

Thanks.
 

Hi,

I think it will remove unused logic. But there should be at least a warning in the log-file.

Kind regards
hqqh
 

Unused combinational logic will be removed automatically. There is a switch that will remove unused sequential logic. Depending on your tool version, the switch may be on or off be default.
 

right, there is options to remove unloaded sequential logic. set compile_delete_unloaded_sequential_cells true
 

it will remove the unused logic, for i used the formality compare the rtl and netlist
,i find ,the implement have lesser logic,the rest have been optimized!
 

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