Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

maximum width in tsmc 0.18um process

Status
Not open for further replies.
K

kumaran_reddy

Newbie level 1
Joined
Jan 23, 2010
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
india
Activity points
1,287
hi all,

what is the maximum width that we can use in tsmc 180nm process..

as per the design equation(thomas lee's book) i got some 437um as width, but ads is giving an error that maximum width is 100um

even after using fingers it comes around 320um..

how to get around this prob or am i missing something here?

please help me out..

thank u all....
 

Hi Kumarn,
You will get exact number from TSMC PDK manual. see Thomas Lee took width of 437 um for 0.25 or 0.6 um process for which he has design CMOS LNA.

But, your process is 0.18 um so, there must be some maximum limit which you can come to know from Design PDK manual.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top