synopsys design constraint

Iam working with soc encounter 8.1
I have a bidirectional buffer in vhdl as follows
-----------------------------------------------------------
entity bidirectional_buffer is

--generic (width : integer := 8);

port (y1 : inout std_logic;

a1 : in std_logic;

e1 : in std_logic;

b1 : out std_logic);

end bidirectional_buffer;
-----------------------------------------------------------------
i was trying to put in few constraints like set_max_delay, set_max_area etc during synthesis of this vhdl file
----------------------------------------------------------------
set sdc_version 1.4
# Set the current design
current_design bidirectional_buffer
set_max_delay -from [get_ports in[b1]] -to [get_ports out[y1]] 2
------------------------------------------------------------------------
But my RTL compiler is not taking up the sdc file.It is showing the following error

Error : Could not interpret SDC command. [SDC-202] [read_sdc]
: The TCL interpreter encountered the following error while processing line '5' of the SDC file 'Desktop/bibuffer/bidir.sdc': invalid command name 'b1'.
: The 'read_sdc' command encountered a problem while trying to evaluate an SDC command. This SDC command will be added to the Tcl variable $::dc::sdc_failed_commands.

Error : A required object parameter could not be found. [TUI-61] [path_group]
: An object of type 'instance|external_delay|clock|port|pin' named '' could not be found.
: Check to make sure that the object exists and is of the correct type. The 'what_is' command can be used to determine the type of an object.
path_group: assigns certain paths to a cost group

Can somebody tell me where is the trouble in the sdc file

It seems like that your SDC file 5th line has a strange port which could not match your design.

was the code synthesised before applying constraints

Hi gharuda

In soc encounter the RTL import is done along with .lib,.sdc and .lef file
Then we do the synthesis
After the synthesis the tool generates 3 fimes with extensions .g,.sdc and .v
Then we import the .v netlist and .sdc at design import for further floor planning ,route etc