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Add pads in verilog netlist

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ksrinivasan

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Hi friends
Can somebody tell me how to manually pads for a verilog netlist
Especially input,output and inout pads
i need correct syntax also
Iam using AMI 0.5 u technology and using cadence soc encounter 8.1 tool
 

Adding pad ring manually is no different from adding any other standard cell manually in your netlist.

So in your netlist, add the following line

pad1 i_pad1 (.outp (outp), .inp (inp)); // where pad1 the pad cell name, i_pad1 is the instance name, outp is the output net name and inp is the input netname. Add the pad in your design.io file for soc encounter.

In additon, you need to provide the path to pad lef file in design.conf file for soc encounter.

Hope it helps.

ebuddy
 

Thats fine
I have done that also
My main problem is with the bidirectional buffer which has inout

inout [31:0] SD_IO, MD_IO;
inout [6:0] CB_IO;
inout [3:0] PB_IO;

For example for SD i have done like this
PADINOUT p00(.DO(SD_IO[31]), .OEN(s3_sys_byte3), .DI(ledcoutdata[7]) ,.YPAD(sddata[31]));

Is this right
 

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