Problem with post simulation using calibre PEX and spectre

Hi, I'm using Calibre PEX and Cadence Spectre to do post-layout simulation of an OPAMP. I'm using Charterd 0.35um technology. The pre-layout simulation is alright and i also passed LVS. But the Post-layout simulation is not correct, the biasing point of these transistors looks weird.
Take a current mirror for example: MP10 and MP0 forms a current mirror, (W/L)10=(30um/3um) and (W/L)0=(120um/3um),MP10 have 3 fingers while MP0 have 10 fingers. In post simulation the id of MP10 is (-8.37424u*3)about 25uA but that of MP0 is (-33.6371u*12) over 400uA, this really puzzles me since their Vdsat are the same and they are all working in saturation, i think the id of MP0 should be about 100uA. Can anbody help me? Thank you

***********************************************
*Pre-layout simulation
***********************************************
string OP("/I3/MP10" "??")
gm 157.24u
id -31.2366u
vds -407.893m
vdsat -295.064m
vgs -1.21116
vth -855.268m

string OP("/I3/MP0" "??")
gm 569.993u
id -120.807u
vds -291.556m
vdsat -295.064m
vgs -1.21116
vth -855.268m
***********************************************
*Post-layout simulation
***********************************************
string OP("/I3/MP10__3@2" "??")
gm 81.9997u
id -8.37424u
vds -295.526m
vdsat -158.418m
vgs -1.02411
vth -855.268m

string OP("/I3/MP0__12@2" "??")
gm 330.044u
id -33.6371u
vds -340.88m
vdsat -158.418m
vgs -1.02411
vth -855.268m

Re: Problem with post simulation using calibre PEX and spect

There's something utterly wrong: the operation points shouldn't change so much from pre- to postLayout sim, but your vgs changed by nearly 200mV! Check your source and bulk connections to VDD, and also check why the primary current into the mirror decreased from 31 to 25µA.

Re: Problem with post simulation using calibre PEX and spect

bellona said:

Hi, I'm using Calibre PEX and Cadence Spectre to do post-layout simulation of an OPAMP. I'm using Charterd 0.35um technology. The pre-layout simulation is alright and i also passed LVS. But the Post-layout simulation is not correct, the biasing point of these transistors looks weird.
Take a current mirror for example: MP10 and MP0 forms a current mirror, (W/L)10=(30um/3um) and (W/L)0=(120um/3um),MP10 have 3 fingers while MP0 have 10 fingers. In post simulation the id of MP10 is (-8.37424u*3)about 25uA but that of MP0 is (-33.6371u*12) over 400uA, this really puzzles me since their Vdsat are the same and they are all working in saturation, i think the id of MP0 should be about 100uA. Can anbody help me? Thank you

Click to expand...

There is something wrong with your estimates.

Transistor MP10 has 3 fingers with W=30 um -> 90 um of gate width.
Transistor MP0 has 12 fingers (or 10?) with W=100 um -> 1200 um gate width.

The current ratio should be 1200/90~13.33.

Why do you expect to see 100 uA current in MP0 if MP10 has 25 uA?


As for Vgs change by ~200mV, the only plausible reason for that is source metal debiasing, which means there are either problem with the layout (too lareg source metal resistance), or problems with parasitic extraction (this happens quite often).

Sorry i didn't make myself clear.
Transistor MP10 has 3 fingers with W=10 um -> 30 um of gate width.
Transistor MP0 has 12 fingers with W=10 um -> 120 um gate width
Hence the ratio 12/3

I have tried PEX with NO R/C, i still got similar results, guess this should rule out problems with layout since I passed LVS with no errors. I think maybe it's caused by parasitic extraction, can you give some suggestion on what might be the cause? (Something i miss in these PEX settings?) Thank you

Re: Problem with post simulation using calibre PEX and spect

bellona said:

Sorry i didn't make myself clear.
Transistor MP10 has 3 fingers with W=10 um -> 30 um of gate width.
Transistor MP0 has 12 fingers with W=10 um -> 120 um gate width
Hence the ratio 12/3

I have tried PEX with NO R/C, i still got similar results, guess this should rule out problems with layout since I passed LVS with no errors. I think maybe it's caused by parasitic extraction, can you give some suggestion on what might be the cause? (Something i miss in these PEX settings?) Thank you

Click to expand...

Please check the following - how the finger devices are recognized - as several instances (fingers), or as one instance?

If the latter is the case, then you do not need to multiply the current by the number of fingers - this current is the total current in a multi-finger device. Then the ratio of the currents is approximately the same as in pre-layout case. I think this should be the case, since your current in MP0 device in post-layout calculations (when you multiply the current by the number of fingers - 12) is much higher than MP0 current in pre-layout simulations - which is obviously wrong (Vgs gets lower and you get IR voltage drop in post-simulation).

Please check this and let us know.

Thank you, I'll look into that. Currently I'm trying to use spectre format rather than calibreview for post-sim, I'll keep this post updated.

The problem is solved, i changed the PEX output format to spectre and everything is alright now. Seems calibreview does not work well with spectre simulator in my case.

I'm using calibre 2008.02 and Cadence ic5141.
Process: Chartered 0.35um 2P4M 3.3V / 5V Salicide
LVS Runset: EDA-CAD-035-LV011 Rev 1J
PEX Runset: EDA-CAD-035-EX025 Rev 1C

I think would be good to post your sim netlist here.
That would help a lot!