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    about cmos fabrication technology

    in cadence i m using umc 180nm technology labrary?can anybody tell me which fabrication tech we are using either nwell/pwell or we are using twin-well process.... plz reply

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    Re: about cmos fabrication technology

    RFMF: Find out from your PDK description! How should we know, which process you are using?



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    Re: about cmos fabrication technology

    i think its using nwell process i m saying it because when i select nmos from pdk we did not get any well for nmos. tell me how can i switch to twin well process. do i need to change whole library which use twin well process????



    •   Alt31st January 2010, 11:19

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    Re: about cmos fabrication technology

    Quote Originally Posted by lokesh garg
    i think its using nwell process i m saying it because when i select nmos from pdk we did not get any well for nmos.
    Right.
    Quote Originally Posted by lokesh garg
    tell me how can i switch to twin well process.
    Ask the foundry.
    Quote Originally Posted by lokesh garg
    do i need to change whole library which use twin well process????
    Of course.



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    Re: about cmos fabrication technology

    i m asking about this question because i m having a problem while doing LVS check. i made a layout of op-amp in UMC 180nm technology library, in which there are two separate pins gnd and vout in my schematic but in layout it is showing both of them connected, thats why it is giving error in LVS check. in one of the post here i read that i m using nwell procell which have same substrate thats why its showing connection between ground and vout. plz tell me what is the reason behind it...... thanks



    •   Alt31st January 2010, 11:53

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    Re: about cmos fabrication technology

    Quote Originally Posted by lokesh garg
    in one of the post here i read that i m using nwell procell which have same substrate thats why its showing connection between ground and vout.
    No, the type of process never ever is the reason for an unintended short-circuit between nodes. This can only result from layout generation, either created by automatic or by human action.

    Quote Originally Posted by lokesh garg
    plz tell me what is the reason behind it...... thanks
    bellona indicated a possible reason (pcell flattening before layout creation).
    Try and find the position of the short cut, then repair it. If you need help, post a clipping of the output stage part of the layout.
    Did you add feedback to your opAmp? If so, also check the connection from vout to the feedback device for a possible GND short.



    •   Alt31st January 2010, 12:16

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    Re: about cmos fabrication technology

    there is no feedback in my circuit and i have checked..... i will give u the snapshot of ckt in some time



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    Re: about cmos fabrication technology

    Quote Originally Posted by lokesh garg
    i think its using nwell process i m saying it because when i select nmos from pdk we did not get any well for nmos. tell me how can i switch to twin well process. do i need to change whole library which use twin well process????
    if your kit is MM/RF, there is triple well option where nmos can be sitting in individual p-well (it is called T well) and pmos can be sitting in n-well.

    cheers



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    Re: about cmos fabrication technology

    can u tell me how to access T-well option, i have MM/RF kit...



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    Re: about cmos fabrication technology

    Quote Originally Posted by lokesh garg
    can u tell me how to access T-well option, i have MM/RF kit...
    the transistors with triple well option are called N_BPW_18_MM and N_BPW_33_MM. Look at their layout, and you can find the Twell. All the other nmos have no well by default, and you need to add contact to the p-sub, which is the default substrate.



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    Re: about cmos fabrication technology

    i m having a prb, my lyaout still have incomplete nets may be i m missing something, can anybody tell me how to connect N+ poly resistor in layout, i m attaching may schematic and layout of resistor that i m using



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    Re: about cmos fabrication technology

    Quote Originally Posted by lokesh garg
    i m having a prb, my lyaout still have incomplete nets may be i m missing something, can anybody tell me how to connect N+ poly resistor in layout, i m attaching may schematic and layout of resistor that i m using
    metal 1 is fine for the plus and neg terminal. you need sub contact for the n-well.



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    Re: about cmos fabrication technology

    in my layout its still saying there are two incomplete nets,but when i run DRC and LVS it says no error. is it possible or anything wrong in this .... plz tell me



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    Re: about cmos fabrication technology

    Quote Originally Posted by lokesh garg
    in my layout its still saying there are two incomplete nets
    Quote Originally Posted by wpchan05
    ... you need sub contact for the n-well.
    Lokesh,
    I don't have the UMC kit, so I don't know in which well your resistor resides, because you didn't explain the layers. In any case you must assign a fixed potential level to the well. If it's an n-well, either VDD or GND=VSS, see your PDK docu, or just try it. If it's a p-well (or a p-well in an n-well - i.e. a T-well), connect it to GND (and the n-well to VDD). Put contacts around the resistor structure - as many as possible - and connect them to the appropriate potential by metal1. This is the necessary 3rd-terminal connection.



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    Re: about cmos fabrication technology

    this is not my question now? DRC and LVS are not giving any type of error but still there are two incomplete nets? is it fine or there is anything wrong in this?



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    about cmos fabrication technology

    dear Lokesh, first make sure that information your are sharing here is not proprietry...

    by d way.. it is bullk contact error.. check ur ERC database.. you must be getting floating nwell error..


    Deepak.



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    Re: about cmos fabrication technology

    Hi Lokesh,

    When you see your schematic there are two seperate ground connections.

    1. VSS connection
    2. gnd connection

    If you check the gnd connection it is connected to the capacitor C1 whose one end is conncted to the VOUT and other to gnd and the bulk to the VSS connection.

    so there must be some other layer(find it out in your pdk) which you should cover the VSS connection or the gnd connection.else it will show as short.hence you are getting short between VOUT and VSS.

    Thanks,
    yaasi



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