joanna_seczkowska
Newbie level 6
I've created schematic using single CLK input.
Then I've changed the input using ibufgds primitive (naturally inputs were renamed to clk_p and clk_n)
Now I want to modify timing constraint to reflect changes. But still there is only clk net available. Moreover there is only clk pin available during floorplanning.
Does anyone know why?
robert
Then I've changed the input using ibufgds primitive (naturally inputs were renamed to clk_p and clk_n)
Now I want to modify timing constraint to reflect changes. But still there is only clk net available. Moreover there is only clk pin available during floorplanning.
Does anyone know why?
robert