skyhorse
Newbie level 5
I am working with a deep submicron BiCMOS technology.
I did some high T measurement on BJT, and the collector-substrate leakage is 75 nA at 200 C and 1.7 uA at 300 C.
One of my workmates has already submitted a bandgap reference ckt using Brokaw cell. My cadence simulation shows that the output is 1.25 V with ~30 ppm from 25 C to 125 C. My target is to find some ckt workable at 200+ C, but my device model is accurate at T range from 25 to 125 C. I guess our bandgap ckt output won't be good at 200 C due to the BJT leakage. Can any ppl give me some suggestion on the "compensation" techniques?
I am also looking for opportunities for high T applications like PA, Mixer etc. Obviously the leakage is an issue there. It is a shame to tell I know nothing in IC design. Is there any simple test circuit for a begginer as a good starting point?
Shorse
I did some high T measurement on BJT, and the collector-substrate leakage is 75 nA at 200 C and 1.7 uA at 300 C.
One of my workmates has already submitted a bandgap reference ckt using Brokaw cell. My cadence simulation shows that the output is 1.25 V with ~30 ppm from 25 C to 125 C. My target is to find some ckt workable at 200+ C, but my device model is accurate at T range from 25 to 125 C. I guess our bandgap ckt output won't be good at 200 C due to the BJT leakage. Can any ppl give me some suggestion on the "compensation" techniques?
I am also looking for opportunities for high T applications like PA, Mixer etc. Obviously the leakage is an issue there. It is a shame to tell I know nothing in IC design. Is there any simple test circuit for a begginer as a good starting point?
Shorse