Fourier
Newbie level 1
I'm considering of designing a near [1] EPP-compliant interface from a PC to a SLIC Si3210 evaluation board. The latter has a digital PCM input/output, both transmitted in serial manner. At this point I'm interested in transmitting data to the SLIC. For this I have found an ancient IC, the 74LS166, which is an 8-bit parallel-in serial-out (PISO) IC.
As for the EPP-specifications, I have read several online articles, including the one at BeyondLogic (**broken link removed**) which shows the timing diagram for reading in and writing out.
At this point I have /many/ questions regarding the specifications found on BeyondLogic.
1) "EPP Data Write Cycle" timing diagram: As for the nWait signal (active low), is the interface supposed to assert the nWait pin and deassert it once data is received?
2) Table 1: The nWait seems to be a good candidate as a hardware interrupt. But when observing Table 1 one will see a specific interrupt pin (pin 10) -- how is the interrupt signal asserted and for how long (the timing diagram shows nothing about Interrupt)?
3) Why do we have nWait and Interrupt anyway? In theory, isn't it possible to have, say nWait, to assert and then de-assert just as the last bit is sent out? In this way, nWait acts as an interrupt thus leaving out the need for the interrupt pin.
4) I suppose that since the 74LS166 IC is only capable of storing 8 bits at the same time, we need to assert nWait for each received byte on the interface, otherwise there's a break in the transmission (ie, the interrupt service routine doesn't know it can send a new byte)?
5) The 74LS166 (& the interface in general) is clock-driven. The Si3210 has an output clock-pin, PCLK, providing between 512 kHz - 8 MHz (I'll use 512 kHz) which I can use to drive the interface. In addition, a synchronisation signal to define the offset of received and transmitted data. However, I /think/ there will be a synchronisation problem because how can I assure data from the computer will arrive exactly within the FSYNC signal or that the first bit is received on a rising edge of PCLK? Is this a problem at all? I can change the offset of received data within FSYNC's timeframe (125 uS), but received data HAS to be within FSYNC.
6) As for transferring data from the SLIC to the PC, according to the timing diagram in "EPP Data Read Cycle", data will be read in the computer on the rising edge of nDataStrobe. Does this mean that data BEFORE the rising edge will not read?
Please forgive me for my ignorance, I am no expert in electronics engineering (I chose computer science instead >_<). I appreciate any answers or hints.
[1]: "near" in the sense that I don't intend to make it fully EPP-compliant as I don't need it, for instance, not all in/out signals are required to be handled.
The whole idea is to transfer the digital PCM signals from the SLIC to the PC, redirect them to the sound card's D/A converter. The SLIC board already has an A/D / D/A converter.
As for the EPP-specifications, I have read several online articles, including the one at BeyondLogic (**broken link removed**) which shows the timing diagram for reading in and writing out.
At this point I have /many/ questions regarding the specifications found on BeyondLogic.
1) "EPP Data Write Cycle" timing diagram: As for the nWait signal (active low), is the interface supposed to assert the nWait pin and deassert it once data is received?
2) Table 1: The nWait seems to be a good candidate as a hardware interrupt. But when observing Table 1 one will see a specific interrupt pin (pin 10) -- how is the interrupt signal asserted and for how long (the timing diagram shows nothing about Interrupt)?
3) Why do we have nWait and Interrupt anyway? In theory, isn't it possible to have, say nWait, to assert and then de-assert just as the last bit is sent out? In this way, nWait acts as an interrupt thus leaving out the need for the interrupt pin.
4) I suppose that since the 74LS166 IC is only capable of storing 8 bits at the same time, we need to assert nWait for each received byte on the interface, otherwise there's a break in the transmission (ie, the interrupt service routine doesn't know it can send a new byte)?
5) The 74LS166 (& the interface in general) is clock-driven. The Si3210 has an output clock-pin, PCLK, providing between 512 kHz - 8 MHz (I'll use 512 kHz) which I can use to drive the interface. In addition, a synchronisation signal to define the offset of received and transmitted data. However, I /think/ there will be a synchronisation problem because how can I assure data from the computer will arrive exactly within the FSYNC signal or that the first bit is received on a rising edge of PCLK? Is this a problem at all? I can change the offset of received data within FSYNC's timeframe (125 uS), but received data HAS to be within FSYNC.
6) As for transferring data from the SLIC to the PC, according to the timing diagram in "EPP Data Read Cycle", data will be read in the computer on the rising edge of nDataStrobe. Does this mean that data BEFORE the rising edge will not read?
Please forgive me for my ignorance, I am no expert in electronics engineering (I chose computer science instead >_<). I appreciate any answers or hints.
[1]: "near" in the sense that I don't intend to make it fully EPP-compliant as I don't need it, for instance, not all in/out signals are required to be handled.
The whole idea is to transfer the digital PCM signals from the SLIC to the PC, redirect them to the sound card's D/A converter. The SLIC board already has an A/D / D/A converter.