sa.vi20
Newbie level 1
Hi everyone!
I'm a basic (extremely basic!) vhdl programmer and I have to implement a 64 bit DFTL (Dynamic Feedthrough Logic addet)Adder code in an FPGA (Spartan 3) with Verilog or VHDL.
Is there some one who has some good example code for a DFTL Adder?
Thank you a lot for you answer
I'm a basic (extremely basic!) vhdl programmer and I have to implement a 64 bit DFTL (Dynamic Feedthrough Logic addet)Adder code in an FPGA (Spartan 3) with Verilog or VHDL.
Is there some one who has some good example code for a DFTL Adder?
Thank you a lot for you answer