How to understand memory specification in Verilog?

memory in verilog

reg [13] RAM [2];

How big this ram actually is?
is it 14bits by 3 slots
or 14x8 slots ?

by incrementing counter we get cell adresses from 0 to 7 and by shifting 1
we get 3 x 14 bit memory ocupation.

What is right?


I thought that it is 14x3 but after studying the fifo verilog code:
https://www.asic-world.com/examples/verilog/syn_fifo.html#Synchronous_FIFO
I found the code:
always @ (posedge clk or posedge rst)
49 begin : WRITE_POINTER
50 if (rst) begin
51 wr_pointer <= 0;
52 end else if (wr_cs && wr_en ) begin
53 wr_pointer <= wr_pointer + 1;
54 end
55 end

Added after 16 minutes:

When I simulate memory in modelsim I get:
for addresses 0,1,2 right value for addrress 3
I 've got x.
I write to memory like:
reg [13:0] memory [2:0]
ptr = (ptr + 1) & 3;
Memory[ptr] = data_in;

then I read it:
output = Memory[ptr -1] + Moemory[ptr];

Modelsim shows only 3 [13:0] values for array
memory, so simple incrementation go out of range.

I checked another topic and it shows standard incrementation is correct:

Re: memory in verilog

First of all you cant specify a RAM like reg[13]RAM[2]

The correct way to specify a RAM is reg [13:0]RAM[0:2];

This RAM is a 3 14 bit word RAM.

So u can address only three locations.

Say suppose u need to design a RAM of 1K of 8 bit RAM the syntax should be

reg [15:0]RAM[0:1023]; and not reg [15:0]RAM[1023:0];

ask me if u have doubt

memory in verilog

HI ,
i have a doubt in memory which is defined...in the above reply...
if the ram is to be designed for 1kb of 8bit then syntax is [7:0]ram[0:1023] right ?
instead of [15:0]ram[0:1023]!!!
i think it is [7:0] instead of [15:0]? :?: :?:

// Declare memory 64x8 bits = 512 bits or 64 bytes total
reg [7:0] memory_ram_d [63:0];
reg [7:0] memory_ram_q [63:0];

Referred link Verilog memory code. Synchronous Random Access Memory (RAM). Testbench memory modeling.