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Can STA be done using Design Compiler ?

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hi everybody,
we have design compiler but we do not have primetime.i have gone through Himanshu Bhatnagar book and it has scripts for DC as well primetime.
can i apply the same scripts in DC for STA.
for time being is it possible to run STA for our design using DC.
thanks
 

DC has a timing engine, but PTs is better and is typically used for STA signoff.
 

Yes and No.

The timing analysis can be done with DC , but timing signoff with Prime Time.

The timing engines in Prime time is very effectice compared to Design compiler(timing engine called Design Time).

//Sam
 

I think STA for pre-CTS netlist is the same for both DC and PT. You should be able to use the same scripts specially for newer DC version

For post-CTS, post-routed netlist, I think you must use PrimeTime specially for clock tree analysis and on-chip-variation timing analysis
 

the STA should be done by PT ,but using DC is also ok, but it's not so accurate!
 

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