santhosh.mandugula
Member level 5
Hello all,
I am doing the layout of Power supply PAD for VDDPST supply (I have 2 supplies VDD and VDDPST of 1.8v and 3.2v). This PAD is used to supply power to the IO's. For this i have used N-type diodes and one MOSCAP (NMOS cap) as shown in the screenshot. As per my understand,
# When some -ve voltage comes then NMOS is OFF and diodes will become FB'd and discharge the -ve supply to the ground.
# When some +ve voltage has given less than 3.2v, then NMOS turned ON and VDDPST will be given as the DIODES will be in RB"d condition.
My doubt is....
1. when supply is -ve, PAD should supply VDDPST, but here it is zero (as per my analyzisation). Is this situation occurs (-ve supply) in real time operation??
2. Is there any chance of VDDPST to go beyond the 3.2v swing, at that time how it works??
Regards,
santhosh
I am doing the layout of Power supply PAD for VDDPST supply (I have 2 supplies VDD and VDDPST of 1.8v and 3.2v). This PAD is used to supply power to the IO's. For this i have used N-type diodes and one MOSCAP (NMOS cap) as shown in the screenshot. As per my understand,
# When some -ve voltage comes then NMOS is OFF and diodes will become FB'd and discharge the -ve supply to the ground.
# When some +ve voltage has given less than 3.2v, then NMOS turned ON and VDDPST will be given as the DIODES will be in RB"d condition.
My doubt is....
1. when supply is -ve, PAD should supply VDDPST, but here it is zero (as per my analyzisation). Is this situation occurs (-ve supply) in real time operation??
2. Is there any chance of VDDPST to go beyond the 3.2v swing, at that time how it works??
Regards,
santhosh
