How are IPs included in the asic flow

How are IPs included in the asic flow
in verilog? while we do synthesis how do we reference it?
difference between soft IP and Hard IP
if we have hard IP, how do we represent it in HDL and get it synthesized.


Thanks in advance.

Soft IP is when the IP vendor supply you with an HDL model of the IP along with SDC for constraining the IP during synthesis. Hard IP is when the vendor supply you with a physical model of the IP for physical implementation along with a timing model for STA, and a verilog or vhdl model for simulation. In both cases you must hand instantiate the IP in your netlist or RTL.

Thank you iwpia50s,

Can you refer me to any simple examples or some docs.

Hard IPs and soft IPs approaches are the two methodologies by which IPs are delivered.

The hard macro method is used to transfer an IP block that has not only the logic implementation but also the physical implementation. In other words, the physical layout of a hard macro IP is finished and fixed in a particular process technology.

So you can say, the biggest advantage of the hard macro approach is optimization. The hard macro block is timing-guaranteed and layout-optimized. The drawback is poor portability since it is already tied to a specific process technology.

Meanwhile, a soft macro IP has only the logic implementation without the layout.

Thus, soft macro IP has excellent portability. It can be synthesized into any ASIC library if the RTL code and design constraint are available. And the drawback of the soft macro approach is the extra work of physical implementation, or layout. Also Compared to hard macro, the verification of soft macro also requires more attention.

For digital IPs, there is another type referred to as netlist IP. Netlist IP has only the gate-level netlist but not the RTL code, mainly for security reasons. The netlist IP can be used for the same process or library, or it can be used for porting and thus mapped into a different process or library.

Typically, IPs with significant analog content are delivered as hard macros since analog IPs are very process and layout sensitive. Digital IPs, on the other hand, can have the flexibility of being “hard” or “soft.”

HTH
--
Shitansh Vaghela

Thanks alot shitansh,

That is quite a bit of explanation. I understood it. one doubt...
if i have IPs (soft, hard, netlist...), how can i introduce in the asic flow and which point i should do? for each kind of IP.

hi shitansh,
by logic implementation of hard macro do you mean the netlist for it?

sree205 said:

by logic implementation of hard macro do you mean the netlist for it?

Click to expand...

Not exactly netlist, logic implementation means RTL code or OFUSCATED IP, or Encrypted or netlist form of IP.