how to reuse operations? Help needed

how to reuse operations?

could anyone correct my codes? Thanks!

Here is a task for reusing operations. In this task you must reuse arithmetic operations as defined below. First you must create a data-flow graph and schedule operations for all the required solution.# Each of your designs performs an algorithm - "o<=c1*i1+i2+i3+c4*i4;".
# Registers (Flip-flops) on the output "o".
# All ports (c1, c4, i1, i2, i3, i4 and o) are 8-bit vectors: unsigned(7 downto 0) (width=8).
# Make four different solutions, where the algorithm is performed reusing following arithmetic units: 2 multiplication units, 3 adders.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reuse_adder is
port (
i1 : in unsigned(7 downto 0);
i2 : in unsigned(7 downto 0);
i3 : in unsigned(7 downto 0);
i4 : in unsigned(7 downto 0);
c1 : in unsigned(7 downto 0);
c4 : in unsigned(7 downto 0);
clk : in std_logic;
rst : in std_logic;
o : out unsigned(7 downto 0));
end entity reuse_adder;

architecture reuse of reuse_adder is
type statetype is (state1,state2,state3);
signal a_add, b_add, c_add: unsigned(7 downto 0);
signal result, o_temp : unsigned(7 downto 0);
signal state : statetype;
signal next_state : statetype;

begin
next_state <= state2 when state = state1 else state1;
a_add <= c1*i1 when state = state1 else i2;
b_add <= i3 when state = state1 else c4*i4;
c_add <= c4*i4 when state= state1 else o_temp;
result <= a_add + b_add + c_add;

o <= o_temp;

process (clk,rst) is
begin
if rst = '1' then
state <= state1;
o_temp <= (others => '0');
elsif clk'event and clk = '1' then
o_temp <= result;
state <= next_state;
end if;
end process;
end architecture reuse;