james09
Newbie level 4
Hey, could anyone provide me some sample solution of Parametrizable Parallel Multiplier?thanks!
draw a picture of 4X4 block multiplier. Especially find out how the carry and sum signals are connected between blocks.
Tasks:
* Create the 1-bit multiplier element. It is recommended to create it as a component to simplify the later usage.
* Create schematics for a NxM -bit parallel block multiplier (N and M bits in, N+M bits out). Assume initially that N=M but try to take into account more generic cases. You must ensure later that NxN multiplier works properly, the more generic case requires a very careful designing and is not part of this exercise.
* Create VHDL description of such a multiplier using generic parameters to define the size of the multiplier, and generate statements ("for ... generate" and/or "if ... generate") to describe the internal structure. Use unsigned types for inputs/outputs.
* Create a testbench which uses asserts to check the functionality of the multiplier with all legal input combinations.
* Simulate the multiplier as a 4x4-bit multiplier. Repeat this for different sizes (6x6 and 4x6 for instance). Is it working in all cases?
* Synthesize it as a 4x4 multiplier. Check the internal structure of different elements. What are the differences and what is causing them?
Some hints:
* Use the multiplier element to perform all calculations - this allows to create very regular structures.
* Use two-dimensional arrays of wires for the same reason (an array of unsigned bit-vectors is a two-dimensional array of std_logic bits).
* Create the 1-bit multiplier element and the generic multiplier as combinatorial functions - clocks and registers make the task only too complicated. The data-flow style is therefore the most natural one.
draw a picture of 4X4 block multiplier. Especially find out how the carry and sum signals are connected between blocks.
Tasks:
* Create the 1-bit multiplier element. It is recommended to create it as a component to simplify the later usage.
* Create schematics for a NxM -bit parallel block multiplier (N and M bits in, N+M bits out). Assume initially that N=M but try to take into account more generic cases. You must ensure later that NxN multiplier works properly, the more generic case requires a very careful designing and is not part of this exercise.
* Create VHDL description of such a multiplier using generic parameters to define the size of the multiplier, and generate statements ("for ... generate" and/or "if ... generate") to describe the internal structure. Use unsigned types for inputs/outputs.
* Create a testbench which uses asserts to check the functionality of the multiplier with all legal input combinations.
* Simulate the multiplier as a 4x4-bit multiplier. Repeat this for different sizes (6x6 and 4x6 for instance). Is it working in all cases?
* Synthesize it as a 4x4 multiplier. Check the internal structure of different elements. What are the differences and what is causing them?
Some hints:
* Use the multiplier element to perform all calculations - this allows to create very regular structures.
* Use two-dimensional arrays of wires for the same reason (an array of unsigned bit-vectors is a two-dimensional array of std_logic bits).
* Create the 1-bit multiplier element and the generic multiplier as combinatorial functions - clocks and registers make the task only too complicated. The data-flow style is therefore the most natural one.
