Need help in timing budget calculation.

Hi,

I am designing a 4 layer pcb which involves a ARM 7 controller and 2 SDRAMs. Stack-up is;

Top layer : Routing
Layer 2 : VCC
Layer 3 : GND
Layer 4 : Routing

Routing parameters are 8/8 mil.

The set-up and hold timings given in the datasheet are as below;

Controller:

Set-up time : 2.24 ns
Hold Time: 0.57 ns
Output delay set-up time : 2.65 ns
Output delay hold time: 0.49 ns

Memory:

Set-up time : 1.5 ns
Hold time : 0.8 ns
Output delay setup time : 3 ns
Output delay hold time : 0.8 ns

The clock is 72 Mhz and it's trace length after routing is 80 mm.

After using above data, we get min. trace length for data / address / controll lines as 132 mm. This calculation was based on formulas found else where on the net.

This seems to wrong because, I have read in many articles that the length of the data/address lines should be matched with the clock. But what we have got is exactly the opposite.

Can any one please tell me whether the above calculation is correct? If not then what is the correct way of calculation.

I am new to high-speed designing and hence not able to decide whether I am moving in the right direction.

Thanks

ak

Hi first, i've never heard about
minimum lenght. Maksimum
lenght are in many cases
demanded by a protocol.
With 75MHz i see no problem
at all if You route it AS clean as
possible. We do joke about that
everything below 200MHz is DC.