james09
Newbie level 4
Traffic Light Controller
Hello,can any one help me to find the right solution and codes? Thanks a lot!
Sketch an algorithmic state chart (ASM) which covers all the legal state transitions of the machine.
Now that you have successfully modeled two different state machines your task is to model a traffic light controller using state machines. Use separate entity/architecture-pairs for the controller and the timer, whereupon you need to decide what kind of controller/timer-interface you need. The interface can be either synchronous or asynchronous, that is, the timer does or does not use the same clock that the controller does. Furthermore, you may reset the timer directly or through the controller/timer interface. Sketch (at home) an algorithmic state machine (ASM) chart which covers all the legal state transitions of the machine.
Then implement your diagram as a VHDL state machine.
Traffic Lights
Features of the controller are the following:
* The architecture contains two concurrent processes. One to compute the next state (signal next_state), and the other to set the computed next state to be the current state (signal curr_state).
* The controller uses an external timer which produces the needed waiting periods. The controller sends requests and receives acknowledgements to/from the timer via a communication channel (= a set of input/output signals).
* There is sensor pair for both the highway and the farm-road. A sensor informs when a vehicle is approaching the crossing.
* Lights are switched first from green through yellow to red and then from red through red-yellow to green in the other road.
* Waiting periods for the timer are:
o A highway light remains at the state green at least for 30 seconds.
o A farm-road light remains at the state green at least for 5 seconds, but no longer than 10 seconds after the highway sensor has become active.
o A light remains at the states yellow and red-yellow for 2 seconds.
o A state where both the highway lights and the farm-road lights are red lasts 2 seconds.
o When the lights are blinking, the state yellow and blank last 0.5 seconds each. The blinking state is controlled by the input signal blink.
The device is thought to drive two traffic lights in a crossing of a highway, and a farm road. The state of a traffic light is controlled by a signal of the enumerated type t_light_color:
TYPE t_light_color IS (blank, red, yellow, redyellow, green)
The state machine has eight legal states as modelled by the enumerated type m_state. The notation gr refers to the state where the highway light is green ('g') and the farm-road light is red ('r'). The notation yr_to_rr, in turn, refers to the state, where the highway light is yellow ('y') and the farm-road light red ('r'), and where the next-state computation schedules both the highway light and the farm-road light to red. The other transition states are interpreted correspondingly.
TYPE m_state IS (gr, rg, yr_to_rr, yr_to_gr, ry_to_rr, ry_to_rg, rr_to_yr, rr_to_ry)
You may add extra states into the above defined type m_state for control purposes, if required.
Regard gr as the initial default state of the controller. The system returns back to the initial state after the blink state and if there are no active sensor. Add an asynchronous reset signal to force the system to go to the initial state.
Create a testbench which ensures all the possible transactions of the controller. Simulate the design. Synthesize at least the traffic light controller module.
Hello,can any one help me to find the right solution and codes? Thanks a lot!
Sketch an algorithmic state chart (ASM) which covers all the legal state transitions of the machine.
Now that you have successfully modeled two different state machines your task is to model a traffic light controller using state machines. Use separate entity/architecture-pairs for the controller and the timer, whereupon you need to decide what kind of controller/timer-interface you need. The interface can be either synchronous or asynchronous, that is, the timer does or does not use the same clock that the controller does. Furthermore, you may reset the timer directly or through the controller/timer interface. Sketch (at home) an algorithmic state machine (ASM) chart which covers all the legal state transitions of the machine.
Then implement your diagram as a VHDL state machine.
Traffic Lights
Features of the controller are the following:
* The architecture contains two concurrent processes. One to compute the next state (signal next_state), and the other to set the computed next state to be the current state (signal curr_state).
* The controller uses an external timer which produces the needed waiting periods. The controller sends requests and receives acknowledgements to/from the timer via a communication channel (= a set of input/output signals).
* There is sensor pair for both the highway and the farm-road. A sensor informs when a vehicle is approaching the crossing.
* Lights are switched first from green through yellow to red and then from red through red-yellow to green in the other road.
* Waiting periods for the timer are:
o A highway light remains at the state green at least for 30 seconds.
o A farm-road light remains at the state green at least for 5 seconds, but no longer than 10 seconds after the highway sensor has become active.
o A light remains at the states yellow and red-yellow for 2 seconds.
o A state where both the highway lights and the farm-road lights are red lasts 2 seconds.
o When the lights are blinking, the state yellow and blank last 0.5 seconds each. The blinking state is controlled by the input signal blink.
The device is thought to drive two traffic lights in a crossing of a highway, and a farm road. The state of a traffic light is controlled by a signal of the enumerated type t_light_color:
TYPE t_light_color IS (blank, red, yellow, redyellow, green)
The state machine has eight legal states as modelled by the enumerated type m_state. The notation gr refers to the state where the highway light is green ('g') and the farm-road light is red ('r'). The notation yr_to_rr, in turn, refers to the state, where the highway light is yellow ('y') and the farm-road light red ('r'), and where the next-state computation schedules both the highway light and the farm-road light to red. The other transition states are interpreted correspondingly.
TYPE m_state IS (gr, rg, yr_to_rr, yr_to_gr, ry_to_rr, ry_to_rg, rr_to_yr, rr_to_ry)
You may add extra states into the above defined type m_state for control purposes, if required.
Regard gr as the initial default state of the controller. The system returns back to the initial state after the blink state and if there are no active sensor. Add an asynchronous reset signal to force the system to go to the initial state.
Create a testbench which ensures all the possible transactions of the controller. Simulate the design. Synthesize at least the traffic light controller module.
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