Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Reg: Issues that Physical designer reports to Synthesis team

Status
Not open for further replies.

nschiku

Newbie level 6
Joined
Sep 1, 2008
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,347
Hi All,
Can someone point to the kind of issues that the physical design team reports to the synthesis team, after the netlist is released to them for entire Physical Flow.


Thanks,
Nik
 

Timing not metting on so and so path because DC had used optimistic delay values, is very common problem PD team reports ....
 

Re: Reg: Issues that Physical designer reports to Synthesis

They will report only setup timing issues ? Also if the respin happens then the synthesis team uses the same wire loads models right, but synthesis team closes the timing in worst case corner right??
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top