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about parasitic capacitor match problem

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lhlbluesky

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in sc-opamp, Cs and Cf must match each other to achieve better resolution;
for ex: a PGA with 4 times rate: 1, 2, 4, 8, and Cs=8C0, Cf=8C0 4C0 2C0 C0, C0 is unit capacitance (250fF). my question is:

1, to get exact match between Cs and Cf, the parasitic of Cs and Cf, we just call them Cs,para and Cf,para , must match also, if Cs/Cf=8, then Cs,para/Cf,para must equal to 8, then (Cs+Cs,para)/(Cf+Cf,para)=8, however, it is very difficult to make Cs,para/Cf,para=8 exactly in layout design, are there any ways to make the parasitic cap Cs,para and Cf,para match each other as close as possible?

2, another problem, i make Cs and Cf in an array (with unit cap C0), and connect them carefully to get better matching, but when i extract the post-netlist, i find that, the parasitic cap for the two branches (positive path and negative path) is not equal, and has a big difference, just make 4X for example, Cf,para=24fF for the positive path, while for the negative path, Cf,para=17.3fF, and so, the circuit resolution gets worse; and for 8X case, Cf,para=35fF for the positive path, while for the negative path, Cf,para=42.1fF, why?
in layout, i have made a symmetrical routing between the cap array, and i believe that , the parasitic cap should be same for the two branches, but in actual, they are different, and have a big difference. i have checked all the routing and they are symmetric indeed, but what's the reason? how to make them exactly equal or approximately equal? pls help me.

except the above reasons, what other reasons can make the circuit resolution worse?

thanks all in advance.
 

lhlbluesky said:
... except the above reasons, what other reasons can make the circuit resolution worse?
Click to expand...
Perhaps the external environment is different? Do you have (dummy) capacitors all around? Could you show a plot of your layout?
 

i have (dummy) capacitors all around the cap array,and i use tower 0.18um 4LM technology, i want to know, what is the source of parasitic capacitor? and which type of parasitic capacitor can we have? and how to increase or decrease them? the cap type is MIM cap -- cmim_hc, the top plate is TOP_M M3 M2, the bottom plate is M3 M2. can anyone can help me? thanks all.
 

lhlbluesky said:
... what is the source of parasitic capacitor?
Click to expand...
Not-intended area and fringing capacitancies to GND and all other (mainly neighbouring) nodes

lhlbluesky said:
and which type of parasitic capacitor can we have?
Click to expand...
Depends on your extraction rules: either par.caps only to GND, or to GND and all other nodes. See your extraction rules file.

lhlbluesky said:
and how to increase or decrease them?
Click to expand...
It's not necessary to in- or decrease them, but to equalize them for each intended cap of the array. This requires utmost symmetrical layout (same distances between all caps, same routing everywhere in between, best-possible distribution of the multiple-C caps, dummies all around in order to keep the same environment at the periphery).

lhlbluesky said:
the top plate is TOP_M M3 M2, the bottom plate is M3 M2.
Click to expand...
? How can M3 & M2 both be top & bottom plates in the same circuit? Do you use inverse-parallel caps?

Rgds, erikl.
 

in actual, i find that, to equalize the parasitic caps is very difficult, and if Cs=2pF, Cf=1pF, but Cspara/Cf,para may not be 1/2, more or less than 1/2, if so, how to change the parasitic cap to make them equalize 1/2?
 

lhlbluesky said:
i find that, to equalize the parasitic caps is very difficult
Click to expand...
True; it is very difficult, one can succeed, however. Takes a long time and needs quite a lot of extraction runs with parasitics' analysis hereafter.

lhlbluesky said:
how to change the parasitic cap to make them equalize 1/2?
Click to expand...
This of course is only possible, if you use an array of unit caps (all the same (quadratic) size, structure, and orientation) : only then it is possible to achieve an extremely good matching of caps and their parasitics. Best possible distribution of the "multiple" caps + (proportionally) equalized connectivity lengths - including the connections to the external circuitry is inevitable.
 

lhlbluesky said:
in sc-opamp, Cs and Cf must match each other to achieve better resolution;
for ex: a PGA with 4 times rate: 1, 2, 4, 8, and Cs=8C0, Cf=8C0 4C0 2C0 C0, C0 is unit capacitance (250fF). my question is:

1, to get exact match between Cs and Cf, the parasitic of Cs and Cf, we just call them Cs,para and Cf,para , must match also, if Cs/Cf=8, then Cs,para/Cf,para must equal to 8, then (Cs+Cs,para)/(Cf+Cf,para)=8, however, it is very difficult to make Cs,para/Cf,para=8 exactly in layout design, are there any ways to make the parasitic cap Cs,para and Cf,para match each other as close as possible?

2, another problem, i make Cs and Cf in an array (with unit cap C0), and connect them carefully to get better matching, but when i extract the post-netlist, i find that, the parasitic cap for the two branches (positive path and negative path) is not equal, and has a big difference, just make 4X for example, Cf,para=24fF for the positive path, while for the negative path, Cf,para=17.3fF, and so, the circuit resolution gets worse; and for 8X case, Cf,para=35fF for the positive path, while for the negative path, Cf,para=42.1fF, why?
in layout, i have made a symmetrical routing between the cap array, and i believe that , the parasitic cap should be same for the two branches, but in actual, they are different, and have a big difference. i have checked all the routing and they are symmetric indeed, but what's the reason? how to make them exactly equal or approximately equal? pls help me.

except the above reasons, what other reasons can make the circuit resolution worse?

thanks all in advance.
Click to expand...

There may be several root causes for wrong results of your parasitic extraction:

1. incorrect PDK and/or extraction rule deck (in particular incorrect technology file - the one describing BEOL stack).

2. Inaccuracy in parasitic extraction tool (one can not and should not use pattern-matching or rule-based parasitic extraction tools for precision analog designs).

We are seeing these sort of problems all the time form our customers, and solving many of these problems using a highly-accurate 3D field-solver (F3D).

Please have a look at these threads, and if you need a help - send me a message:
 

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