vijay82
Member level 2
Verilog event ordering
What will be the order of execution (and why) of the following two Verilog statements...
1. assign x = <some code involving asynchronous signals>;
2. always @(posedge clk)
if(x == 1'b1)
y <= 1'b1;
(y is 0 before the posedge)
...assuming that x is assigned to 1 at the same time as the clk is going to 1? (And as a consequence of the ordering, y will either remain 0 or become 1)
Also, will the order change for different simulators?
One explanation which satisfies the behaviour with my simulator (ModelSim) is that in the same time slice, blocking statements have the highest priority for being in the active queue; thus x will be 1 first, flop condition will be taken to be true and then the y flop will take a new value 1. All this in the simulator world..
If you think of it in terms of how it will synthesise, x will be the output of a combinational cloud going into the d input of the flop. Thus it will have to satisfy the setup time of flop, which it will not, considering I have specified x to become 1 simultaneously with the clock's rising edge. Thus at the rising edge, x is still 0 (0 having satisfied setup time) and y will retain its old value 0.
What is the correct line of thinking? Is there any other?
What will be the order of execution (and why) of the following two Verilog statements...
1. assign x = <some code involving asynchronous signals>;
2. always @(posedge clk)
if(x == 1'b1)
y <= 1'b1;
(y is 0 before the posedge)
...assuming that x is assigned to 1 at the same time as the clk is going to 1? (And as a consequence of the ordering, y will either remain 0 or become 1)
Also, will the order change for different simulators?
One explanation which satisfies the behaviour with my simulator (ModelSim) is that in the same time slice, blocking statements have the highest priority for being in the active queue; thus x will be 1 first, flop condition will be taken to be true and then the y flop will take a new value 1. All this in the simulator world..
If you think of it in terms of how it will synthesise, x will be the output of a combinational cloud going into the d input of the flop. Thus it will have to satisfy the setup time of flop, which it will not, considering I have specified x to become 1 simultaneously with the clock's rising edge. Thus at the rising edge, x is still 0 (0 having satisfied setup time) and y will retain its old value 0.
What is the correct line of thinking? Is there any other?