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[SOLVED] Event ordering b/w blocking and non-blocking assignments

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vijay82

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Verilog event ordering

What will be the order of execution (and why) of the following two Verilog statements...

1. assign x = <some code involving asynchronous signals>;

2. always @(posedge clk)
if(x == 1'b1)
y <= 1'b1;

(y is 0 before the posedge)

...assuming that x is assigned to 1 at the same time as the clk is going to 1? (And as a consequence of the ordering, y will either remain 0 or become 1)

Also, will the order change for different simulators?

One explanation which satisfies the behaviour with my simulator (ModelSim) is that in the same time slice, blocking statements have the highest priority for being in the active queue; thus x will be 1 first, flop condition will be taken to be true and then the y flop will take a new value 1. All this in the simulator world..
If you think of it in terms of how it will synthesise, x will be the output of a combinational cloud going into the d input of the flop. Thus it will have to satisfy the setup time of flop, which it will not, considering I have specified x to become 1 simultaneously with the clock's rising edge. Thus at the rising edge, x is still 0 (0 having satisfied setup time) and y will retain its old value 0.

What is the correct line of thinking? Is there any other?
 

The question hasn't to do with blocking versus non-blocking statements in my opinion. Generally, there's no specified execution order of continuous assignment among each other or related to procedural blocks. Execution order only applies inside procedural blocks.

It's also not clear, if you are refering to functional (RTL) or timing (gatelevel) simulation. The mentioned setup times would only apply in timing simulation, but than it would be meaningless to say two events are happening at the same time. They actually don't in a real system.
 

FvM said:
The question hasn't to do with blocking versus non-blocking statements in my opinion. Generally, there's no specified execution order of continuous assignment among each other or related to procedural blocks. Execution order only applies inside procedural blocks.
Understood about execution/assignment order being relevant inside or among procedural blocks. But how else would the said piece of code be analysed for the final value of y? Clearly both share a common signal (x) and the output of the circuit would depend on what the simulator algorithms are wrt event ordering. In other words, at posedge clk, what should x be evaluated as? And wouldn't the answer directly lead to a conclusion of which of blocking or non-blocking is executed first?
FvM said:
It's also not clear, if you are refering to functional (RTL) or timing (gatelevel) simulation. The mentioned setup times would only apply in timing simulation, but than it would be meaningless to say two events are happening at the same time. They actually don't in a real system.
Sorry I was referring to functional simulation. It just occurred to me that in the 2nd argument above (thinking of the circuit in terms of hardware), hold time for x=0 would be violated and so there really is no point in analysing it further. What I'm interested in is the functional behaviour, which is what led me to the question in the first place. The first statement is actually part of a testbench while the second is of the DUT - I was surprised to see that y goes high at the same time as x does whereas till now, I would have expected the flop to register x a clock cycle later.
 

O.K., in functional simulation, you can assert x and clk simultaneously. My understanding of Verilog rules is, that
the "execution order" respectively the state of y isn't specfied, so it can be different with different simulators or
even in different simulation runs. In practice, ModelSim will have a particular method of evaluating the simulation
results, but you shouldn't rely on it.

By the way, there's no non-blocking assignment in your code.
 

Final confirmed answer:

-Functional simulation: this is a race condition.
-Gate-level simulation: 'X' will be driven out of the flop.
-Hardware: Flop will go metastable.
 

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