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Help about Current mirror designed use subthreshold mos

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youyang

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Hi all,
What should be taken into account in designing a current mirror using subthreshold pmos, where Vds > 5*VT(26mv)?

Since the Vgs's control on Ids is much more stronger in subthreshold area than in saturate area, the current copy performance of current mirror using subthreshold pmos is better than using saturate pmos, is that correct?

Secondly, the gm reducing in subthreshold area does not matter in current mirror design.

What eles should be taken into account in this design?
 

Hi youyang,

1) If talk about output resistance, it can be expressed as Rds=Va/Ids, where Va=Coeff*L. In this connection Rds is independent from inversion level.
2) Because Ids is more sensitive to Vgs the current mirror based on devices operating at weak inversion (sub-threshold) suffers from increased mismatch and noise comparing with strong/moderate inversion realization.
3) Gm can be a matter in constrained design e.g. high frequency operation where Gm/Cg is important.
4) You can simply consider its as an amplifier (current input, current output): mismatch (offset), noise, freq. performance, input/output resistances etc.
 

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    youyang

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Hi DenisMark,

Among Vinput,Voutput,mismatch,and output impedance, I agree with you that anti-mismatch and anti-noise should be the big problemes in this design.

BTW, Thanks for your reference attached.

DenisMark said:
Hi youyang,

1) If talk about output resistance, it can be expressed as Rds=Va/Ids, where Va=Coeff*L. In this connection Rds is independent from inversion level.
2) Because Ids is more sensitive to Vgs the current mirror based on devices operating at weak inversion (sub-threshold) suffers from increased mismatch and noise comparing with strong/moderate inversion realization.
3) Gm can be a matter in constrained design e.g. high frequency operation where Gm/Cg is important.
4) You can simply consider its as an amplifier (current input, current output): mismatch (offset), noise, freq. performance, input/output resistances etc.
Click to expand...
 

Hi,

Have anybody read the paper "MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design", in which the auther links the 'mismatch' with 'gm/Id' rather than just device's operation area.?

He finds that for a given Id, the mismatch improved with a increasing gm/Id which reaches its peak in Moderate Inversion area.

Have anybody had pratical expericenc about his finding? Or, just give some commons on it!

Thanks
 

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